Voltage-mode sense amplifiers include a pair of cross-coupled inverters to form a latch. The regenerative feedback in the latch provides advantageous speed with regard to sensing high-data-rate input data. Voltage-mode sense amplifiers are thus commonly used in a wide range of data transmission applications. To respond to a differential data input signal, a voltage-mode sense amplifier includes a differential pair of transistors whose gates are driven by the differential data input signal. Depending upon the binary state of the differential data input signal, one of the drain terminals for the differential pair of transistors will slew faster towards ground than the other. The drain terminals couple to the inputs for the cross-coupled pair of inverters. The positive feedback through the cross-coupling of the inverters causes one of the inverter outputs to quickly charge to the power supply voltage whereas the other inverter output is discharged.
Although a voltage-mode sense amplifier is capable of advantageous speed with regard to evaluating the differential data input signal, a differential pair of transistors can never be manufactured to be perfectly matched to each other. The latch has a similar imbalance. The resulting circuit imbalances effectively creates a voltage offset with regard to the response of the differential pair of transistors even if there is no differential input voltage across the gates of the differential pair of transistors. In other words, even with the differential input voltage being zero, it is as if the offset voltage is impressed across the gates of the differential pair of transistors such that the voltage-mode sense amplifier favors one binary output state over the other. This offset voltage can be as much as 20 mV or even 50 mV or higher. Such a level of offset voltage is problematic because the differential input voltage tends to drop as the data rates are pushed ever higher—for example, a voltage-mode sense amplifier may have to make a bit decision based upon a differential data input signal having an amplitude swing of as little as 10 mV. The presence of a 20 mV offset voltage would thus thwart the sensing of such a differential input voltage.
It is thus conventional to null the offset voltage for a voltage-mode sense amplifier. For example, it is known to incrementally switch on additional transistors to boost the weaker transistor in the differential pair. These additional transistors connect between the drain and source of the boosted transistor and are switched on regardless of the binary state for the input data signal. Alternatively, an additional differential pair may be coupled in parallel with the original differential pair of transistors. A voltage DAC biases the gates of the additional differential pair of transistors in a technique denoted as a two-port differential adjustment.
Although these existing offset calibration techniques null the offset voltage, the drain terminals of the differential pair are then saddled with parasitic capacitance. This parasitic capacitance slows down the slew rate for the drain terminals, which is problematic for high-speed data evaluation. Accordingly, there is a need in the art for improved offset nulling for high-speed sense amplifiers.